Semiconductor power devices having trenched gate structure, including trench MOSFET (metal oxide semiconductor field effect transistor), trench IGBT (insulated gate bipolar transistor) or trench Schottky rectifier, are usually used in switching-mode power supplies and in other high switching speed applications. Apart from the device configuration in an active area, a design of a termination area structure of the semiconductor power devices plays an increasingly vital role to maintain breakdown voltage of the semiconductor power devices. Meanwhile, there is still a need to reduce the manufacturing cost and to simply the manufacturing process to meet the requirement for mass production. Therefore, in view of so, U.S. Pat. Nos. 6,309,929, 6,396,090, 6,855,986 and 7,612,407 disclose several device configuration and manufacturing method to make semiconductor power devices with a termination area having trenched field plate which is formed into a space-like gate structure by doing dry poly-silicon etch.
FIG. 1A is a cross-sectional view of an N-channel trench MOSFET with a termination area 100 disclosed in the prior art of U.S. Pat. No. 6,396,090, which is formed in an N− epitaxial layer 101 extending onto a semiconductor N+ substrate 102 which is coated with a drain metal on a rear side. The termination area 100 further comprises: a wide termination trench 103 formed in the N− epitaxial layer 101; a spacer-like gate structure 104 padded by a gate oxide layer 105 and formed only along a trench sidewall of the wide termination trench 103; an inter-conductive oxide layer 106 covering surface of the spacer-like gate structure 104; a termination oxide layer 107 formed in the wide termination trench 103 to define a contact area for a source metal to contact with an active area. On the other hand, according to the prior art, a body mask is saved because that the silicon layer for the P body region 108 is epitaxially formed without requiring a body mask.
FIG. 1B is a cross-sectional view of a trench Schottky rectifier disclosed in U.S. Pat. No. 6,309,929 with a termination area 110 which is formed by a similar method to that of FIG. 1A, wherein the termination area structure 110 also comprises a spacer-like gate structure 114 padded by a gate oxide layer 115 and located only along a trench sidewall of a wide termination trench 116. As for the trench Schottky rectifier, there is no an inter-conductive oxide layer (as the inter-conductive oxide layer 106 in FIG. 1A) covering the surface of the spacer-like gate structure 114 as to provide a contact between an anode metal and the spacer-like gate structure 114.
FIG. 1C is a cross-sectional view of another trench Schottky rectifier with a termination area 120 disclosed in U.S. Pat. No. 6,855,593. Comparing with the termination area 110 in FIG. 1B, the termination area 120 comprises a gate oxide layer 121 along whole trench bottom and trench sidewall of a wide termination trench 122 which is not extended to a device edge (illustrated by a scribe line), onto the gate oxide layer 121, a spacer-like gate structure 123 is formed along the trench sidewall on both sides of the wide termination trench 122 in view of the cross-sectional drawing, and exposing a part of the trench bottom of the wide termination trench 122.
The termination area structure comprising the wide termination trench and the spacer-like gate structure aforementioned do have the capability of preventing voltage breakdown phenomena from premature without requiring an extra cost which is superior to other conventional termination area structures known to those having skill in the art. However, when making a trench MOSFET with a termination area using the aforementioned configuration and method, for example in FIG. 1A, a pronounced problem comes out that the P type semiconductor layer for the P body region 108 is formed epitaxially before etching a plurality of trenches 109 in the active area to save a body mask as discussed above, causing Boron segregation along trench sidewalls of the trenches 109 in the active area during a growth step for a sacrificial oxide (not shown) and for the gate oxide layer 105 and leading to undesirable punch-through vulnerabilities. The punch-through issue becomes more pronounced when cell pitch of the semiconductor power device is decreased less than 2.0 um.
In order to overcome the punch-through issue, another semiconductor power device with a termination area structure 130 is disclosed in U.S. Pat. No. 7,612,407 wherein the body region is formed by an ion implantation step after forming a plurality of trenches, as shown in FIG. 1D. The termination area structure 130 comprises an oxide layer 131 formed in middle of a spacer-like gate structure 132 in a wide termination trench 133 before the ion implantation process for formation of the P body region 134. Therefore, the P body region 134 will not be disposed below trench bottom of the wide termination trench 133 because the oxide layer 131 is acting as a body ion implantation blocking layer, sustaining a high breakdown voltage in the termination area structure 130. However, there is an extra cost for depositing and CMP (Chemical Mechanical Polishing) the oxide layer 131, which is not conductive to mass production.
Therefore, there is still a need in the art of the semiconductor power device design and fabrication, particular in the termination area, to provide a novel cell structure, device configuration and fabrication process that would further resolve the problems discussed above.